`timescale 1ns / 1ps

`include "MIPSCPU_COMMON.vh"

module SpecialRegister(
	rst,
	clk,
	pc_write_enable,
	pc_written_value,
	hi_write_enable,
	hi_written_value,
	lo_write_enable,
	lo_written_value,
	pc_value,
	hi_value,
	lo_value
    );

	input rst, clk;
	input pc_write_enable, hi_write_enable, lo_write_enable;
	input[`DATA_WIDTH - 1 : 0] pc_written_value, hi_written_value, lo_written_value;
	output reg[`DATA_WIDTH - 1 : 0] pc_value, hi_value, lo_value;
	
	always @(negedge rst or negedge clk)
	begin
		if (!rst) begin
			pc_value <= 0;
			hi_value <= 0;
			lo_value <= 0;
		end else if (!clk) begin
			if (pc_write_enable)
				pc_value <= pc_written_value;
			if (hi_write_enable)
				hi_value <= hi_written_value;
			if (lo_write_enable)
				lo_value <= lo_written_value;
		end
	end

endmodule
